Electronic circuit components and systems have become increasingly complex and the design of these components and systems has correspondingly become more time consuming, complex and subject to increasingly higher failure rates. The prior methods of making electronic circuits has led to problems in testing and manufacturing, since the act of prior art connections of the devices may cause failure of the otherwise acceptable device. Soldering temperatures and conditions used in the fabrication of prior art circuitry lead to occasional failures and inadequate conductor joints. These problems may not be discoverable in prior devices until after the device is completely assembled. With prior art systems, the integrity of the mounting connections to the devices is difficult to verify. Wire wrap techniques are time consuming and require the conductors from the devices to either be individually connected to respective conductors, or to pierce a "flex" which contains reconfigured conductors to establish the desired circuitry.
Prior art techniques for the assembly of electronic devices presently call for preparation of a substrate containing the wiring, such as a printed circuit board or the like, upon which the devices, such as chips, capacitors, resistors, inductors, subassemblies, digital or analog devices in the form of packaged or bare die, multichip modules, hybrid devices and the like, are directly mounted, usually by the use of a soldering technique or other method to achieve a secure contact. In design, assembly and use, including maintenance and upgrades, devices which are assembled cannot be easily disassembled without damage, and therefore when found defective or upon failure, the entire assembly must be replaced and discarded. Reassembly and reuse of such devices has not generally been practical nor economical. Recall of significant components of computers when a design flaw is discovered has heretofore resulted in the discard of significant quantities of otherwise useful devices at great cost.
Materials and structures well suited for the manufacture of wiring are frequently ill suited to the creation of a durable, robust device mounting surface.
Conversely, materials which are well adapted to forming a device mounting surface make poor wiring. Any changes needed in the number of devices, their type or location requires a new wiring structure and any testing or burn in of the devices must be redone.
Mounting devices on wiring makes disassembly difficult because such manipulation will frequently damage the devices, the wiring or both. Structures which allow routine dismounting of devices are generally unsuited to the fabrication of wiring. Conversely, structures particularly suitable for creation of wiring do not lend themselves to be mounting on devices for both structural and materials of composition considerations. Device mounting frequently involves temperature, physical forces, and chemical reactants which can damage wiring. Consequently, wiring must be constructed with protective coverings or be made excessively robust to withstand assembly with and disassembly from the devices.
For devices mounted on wiring, the wiring must supply the physical structure to hold and protect the devices.
Because of the aforementioned problems the prior art wiring and device assemblies do not lend themselves to changes and retrofits during design and production or to field upgrades and maintenance.
Similarly, unification of device and wiring in prior devices results in limited access at all phases of design, production, quality control and use for troubleshooting and testing of the devices. Prior art cabling between electronic assemblies is generally fixed in nature and not easily reconfigured.
Attempts to solve these and other problems have been evolved only for the design and prototype phase and are unsuitable for production quantities of devices for reasons of cost, structures and signal integrity, As a result, prior efforts have resulted in most cases in a prototype-only technology.
In electronic circuits, the active circuit elements are connected to each other with wires or other electronic conductors. These connections among elements are known as interconnect. In the past, the performance and cost of the whole electronic system was mostly determined by the design of the active devices. However as system performance has increased and size has been reduced, the interconnect has had to become more sophisticated. Today, the cost of all of the different levels of interconnect is at least as great as the cost of the active elements, and the performance of the whole system now depends critically on the design of the interconnect.
Ball grid arrays are well known in which packaged integrated circuit chips are mounted on a surface of a substrate, and electrical connection to electrically conductive materials not a part of the packaged integrated circuit, such as a printed circuit board, is made by an array of solder balls located on a surface of the substrate opposite the surface to which the devices are attached. Passive components such as resistors or capacitors can also be mounted on the top surface of the substrate. The substrate can be a multi-layer structure, electrically conductive traces and or regions being formed on a surface of each layer of the substrate, such as is described in U.S. Pat. No. 4,976,761 to Chu. The integrated circuit chip or chips and the passive components are typically encapsulated in plastic to protect the chip or chips from the external environment. The chips are electrically connected to the substrate by wirebonding, tape automated bonding, or flip-chip interconnection. Ball grid arrays allow a high density of external chip connections to be made as compared to other packaged integrated circuits having leads extending from the package.
When interconnect for electronic systems is designed, there are three major areas of concern. First is the signal fidelity that can be provided by the interconnect. This encompasses the electrical characteristics of the conductors, and includes resistance, capacitance and inductance. In modern electronic systems, the signal delay from pin to pin is increasing in importance. It is desirable to minimize the delay. It is also important that the delay be known, and in some systems it is important to be able to predict the delay. Another aspect of signal quality which is important is cross-talk between conductors. Cross-talk is the lack of isolation of one signal from another. In prior art systems, whenever performance issues dictated a revised routing to eliminate cross talk, even if there was no need to change the devices, a new wiring had to be created and the testing and burn in repeated.
The second major interconnect design criteria is size. This includes the total number of pin-to-pin connections that can be achieved; the physical size of the interconnect; the density of the interconnect in connections per unit space; and the routability of the connections. Routability is the ability to electrically connect all given pins to any other pins as required by the design. Most interconnect systems are not 100% routable because there are limitations, or rules, constraining the connections between selected pins. Another aspect of size is scalability. This is the ability of an interconnect method to be practical across a wide range of production quantities. If the interconnect method must be changed as a given system increases production quantities, there is significant risk that the function and/or performance of the high-volume method will be different from that of the low-volume one.
The third major interconnect design criteria is cost. This is closely tied to both production quantity and the time required to complete the design. The ideal interconnect method can promptly deliver parts after each stage of the design, at low cost, and can then continue to provide parts at competitive cost as production quantities increase into the thousands. The amount and type of equipment required in manufacturing has a large effect on cost. The time that it takes to manufacture the interconnect generally increases with cost. Rapid part delivery is desirable so that product development cycles can be shortened and redesigns can occur more quickly.
There are two broad methods of creating conductors. In one, the conductors are produced after the design is created. An example of this approach is the etching of the conductors on a printed circuit board. The second approach is to produce the conductors prior to the design and create the conductors by removing the material not required by the design.
A number of approaches have come to be used in an attempt to satisfy all of the ideal design criteria. All approaches must in some way deal with the problem of manufacturing the complexity which is inherent to interconnect. One way to deal with the complexity is to make a single complicated structure, such as a photomask, which is then easily replicated. Interconnect manufactured in this way includes printed circuit boards, most multi-chip modules, hybrid circuits, on-chip wiring, and lead frames. Because the manufacture of the initial complex structure is expensive, all interconnect manufactured in this way suffers from the critical disadvantage that it is very expensive and time consuming to produce in small quantities. This means that prototypes can not be quickly and economically produced using these techniques.
The other major way in which the inherent interconnect complexity is manufactured is through a simple step by step method for creating complex structures. Present examples of this approach are field-programmable logic devices (FPLD), field-programmable gate arrays (FPGA), cross-point switches, fuses, anti-fuses, wire bonds, wire wrap, emulators, direct write e-beam, laser deposition, ion-milling, and thick-film ink jet writing. All of these methods use some structure whose easily modified placement or configuration creates the particular pattern of connections required for a given design. Those approaches which route the signals through active devices or non-homogeneous conductors suffer from signal fidelity problems. Generally signal delay is long or resistance is high. The approaches which use homogeneous conductors (wire bonds, wire wrap) suffer from limitations of size. They are useful only for relatively small numbers of connections and are relatively expensive to produce in large quantities.
There are techniques for creating interconnect which hybridize the two ways for creating complexity. An example of this is laser-programmed gate arrays. These circuits are built nearly to completion using standard photomasks, then the last few layers of interconnect are patterned using a laser. The laser is used to disrupt unwanted connections in a metal pattern which connects each node to every other node on the die. While useful, this does not offer a broad solution to the general interconnect problem. The system designer is constrained by the design of the base gate array, the interconnect does not span more than one integrated circuit, and the interconnect is monolithic with the active devices. In monolithic devices, the manufacturing steps for the active devices are followed by the manufacture of the interconnect, all on the same physical structure. Thus if a defect occurs in either, the whole device is defective. This limits the yield with increasing scale, and hence raises the cost of monolithic devices. Another limitation of monolithic devices is that the interconnect can not be separated from the active devices after manufacturing for repair or redesign.
While all of these techniques provide advantages in the manufacture of electronic interconnect, none satisfy all of the needs for rapid manufacture of low-cost, high pin count, high signal quality interconnect, including: large number of connections, low resistance, controlled impedance, high routability, short propagation delay, low cost in quantity one, and the ability to change the connections with minimal expense or delay. Similarly, access for testing is inhibited by the permanent and direct mounting of the devices on wiring in the prior art systems.